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rev. 1.01 november 2007 ddr2 sdram k4t51163qe * samsung electronics reserves the right to chan ge products or specification without notice. information in this document is provided in relation to samsung products, and is subject to change without notice. nothing in this document shall be construed as granting any license, express or implied, by estoppel or otherwise, to any intellectual property rights in samsung products or technology. all information in this document is provided on as "as is" basis without guarantee or warranty of any kind. 1. for updates or additional information about sams ung products, contact your nearest samsung office. 2. samsung products are not intended for use in life suppor t, critical care, medical, sa fety equipment, or similar applications where product failure couldresult in loss of life or personal or physical harm, or any military or defense application, or any governm ental procurement to which special terms or provisions may apply. 512mb e-die ddr2 sdram specification 84fbga with pb-free (rohs compliant) industrial temp.
rev. 1.01 november 2007 ddr2 sdram k4t51163qe revision history revision month year history 1.0 april 2007 - first release revision 1.0 1.01 november 2007 - corrected typo of package dimension
rev. 1.01 november 2007 ddr2 sdram k4t51163qe key features speed ddr2-800 6-6-6 ddr2-667 5-5-5 ddr2-533 4-4-4 ddr2-400 3-3-3 units cas latency 6 5 43 tck trcd(min) 15 15 15 15 ns trp(min) 15 15 15 15 ns trc(min) 60 60 60 55 ns ordering information note : 1. speed bin is in order of cl-trcd-trp 2. rohs compliant 3. ?i? of part number(12th digit) stand for industrial temp./normal power products 4. ?p? of part number(12th digit) stand for industrial temp./low power products 5. ?d? of part number(12th digit) stand for industrial temp./super low power products org. ddr2-800 6-6-6 ddr2-667 5-5-5 ddr2-533 4-4-4 ddr2-400 3-3-3 package 32mx16 k4t51163qe-zif7 k4t51163qe-zie6 k4t51163qe-zid5 k4t51163qe-zicc 84 fbga k4t51163qe-zpf7 k4t51163qe-zpe6 k4t51163qe-zpd5 k4t51163qe-zpcc k4t51163qe-zde6 ? jedec standard 1.8v 0.1v power supply ? vddq = 1.8v 0.1v ? 200 mhz f ck for 400mb/sec/pin, 267mhz f ck for 533mb/sec/ pin, 333mhz f ck for 667mb/sec/pin, 400mhz f ck for 800mb/ sec/pin ?4 banks ?posted cas ? programmable cas latency: 3, 4, 5 ? programmable additive latency: 0, 1 , 2 , 3 and 4 ? write latency(wl) = read latency(rl) -1 ? burst length: 4 , 8(interleave/nibble sequential) ? programmable sequential / interleave burst mode ? bi-directional differential data-strobe (single-ended data- strobe is an optional feature) ? off-chip driver(ocd) impedance adjustment ? on die termination ? special function support -pasr(partial array self refresh) -50ohm odt -support industrial temp .(case temp. -40 to 95 c) ? average refresh period 7.8us at -40 c < t case < 95 c ? all of lead-free products are compliant for rohs the 512mb ddr2 sdram is organized as a 8mbit x 16 i/os x 4 banks device. this synchronous device achieves high speed dou- ble-data-rate transfer rates of up to 800mb/sec/pin (ddr2-800) for general applications. the chip is designed to comply with the following key ddr2 sdram features such as posted cas with additive latency, write latency = read latency -1, off-chip driver(ocd) impedance adjustment and on die termination. all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. inputs are latched at the crosspoint of differenti al clocks (ck rising and ck falling). all i/os are synchronized with a pair of bidirectional strobes (dqs and dqs ) in a source synchronous fashion. the address bus is used to convey row, column, and bank address information in a ras / cas multiplexing style. the 512mb ddr2 device operates with a single 1.8v 0.1v power supply and 1.8v 0.1v vddq. the 512mb ddr2 device is available in 84ball fbgas(x16). note: the functionality described and the timing specifications included in this data sheet are for the dll enabled mode of oper- ation. note : this data sheet is an abstract of full ddr2 specificat ion and does not cover the common features which are described in ?samsung?s ddr2 sdram device operation & timing diagram?
rev. 1.01 november 2007 ddr2 sdram k4t51163qe package pinout/mechanical dimension & addressing x16 package pinout (top view) : 84ball fbga package a b c d e f g h j k l vdd nc vss dq6 vssq ldm vddq vddq vddq vssq vssq ldqs ldqs dq7 dq0 vddq dq2 vssq dq5 vssdl vdd ck ras ck cas cs a2 a6 a4 a11 a8 nc nc nc a12 a9 a7 a5 a0 vdd a10/ap vss vddq vssq dq1 dq3 dq4 vddl a1 a3 ba1 vref vss cke we ba0 vdd vss vdd nc vss dq14 vssq udm vddq vddq vssq dq9 dq11 dq12 vddq vddq vssq vssq udqs udqs dq15 udq0 vddq dq10 vssq dq13 nc odt m n p r note : 1. vddl and vssdl are power and ground for the dll. 2. in case of only 8 dqs out of 16 dqs are used, ldqs, ldqsb and dq0~7 must be used. + + + + + + + + + + + 123456789 a b c d e f g h j k l + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + m n p r + + + + + + : populated ball + : depopulated ball top view ball locations (x16) (see the balls through the package) 123 789
rev. 1.01 november 2007 ddr2 sdram k4t51163qe fbga package dimension (x16) b c d e f g h j k l a 9.00 0.10 6.40 0.80 1.60 # a1 index mark 0.80 x 8 = 1 2 3 4 5 6 7 8 9 3.20 13.00 0.10 0.80 0.80 0.80 11.20 x 14 = 5.60 (0.95) (1.90) 84- ? 0.45 solder ball 0.2 m ab (post reflow 0.50 0.05) (datum a) (datum b) a b molding area 9.00 0.10 0.10max 0.35 0.05 1.10 0.10 bottom top 13.00 0.10 m n p r #a1
rev. 1.01 november 2007 ddr2 sdram k4t51163qe input/output functional description symbol type function ck, ck input clock: ck and ck are differential clock inputs. all address and cont rol input signals are sampled on the crossing of the positive edge of ck and negative edge of ck . output (read) data is referenced to the crossings of ck and ck (both directions of crossing). cke input clock enable: cke high activates, and cke low deactivates, inte rnal clock signals and device input buffers and out- put drivers. taking cke low provides precharge power-down and self refresh operation (all banks idle), or active power-down (row active in any bank). cke is synchronous for power down entry and exit, and for self refresh entry. cke is asynchronous for self refresh exit. after v ref has become stable during the power on and initialization swquence, it must be maintained for proper operation of the cke receiver. for proper self-refresh entry and exit, v ref must be maintained to this input. cke must be maintained high throughout read and write accesses. input buffers, excluding ck, ck , odt and cke are disabled during power-down. i nput buffers, excluding c ke, are disabled during self refresh. cs input chip select: all commands are masked when cs is registered high. cs provides for external rank selection on sys- tems with multiple ranks. cs is considered part of the command code. odt input on die termination: odt (registered high) enables terminat ion resistance internal to the ddr2 sdram. for x16 configuration odt is appl ied to each dq, udqs/udqs , ldqs/ldqs , udm, and ldm signal. the odt pin will be ignored if the extended mode register (e mrs(1)) is programmed to disable odt. ras , cas , we input command inputs: ras , cas and we (along with cs ) define the command being entered. dm input input data mask: dm is an input mask signal for write data. input data is masked when dm is sampled high coinci- dent with that input data during a write access. dm is sampled on both edges of dqs. although dm pins are input only, the dm loading matches the dq and dqs loading. ba0 - ba1 input bank address inputs: ba0 - ba1 define to which bank an active , read, write or precharge command is being applied. bank address also determines if the mode register or extended mode register is to be accessed during a mrs or emrs cycle. a0 - a13 input address inputs: provided the row address for active commands and the column address and auto precharge bit for read/write commands to select one location out of the memo ry array in the respective bank. a10 is sampled during a precharge command to determine whether the precharge applies to one bank (a10 low) or all banks (a10 high). if only one bank is to be precharged, the bank is selected by ba0, ba1. the address inputs also provide the op-code dur- ing mode register set commands. dq input/out- put data input/ output: bi-directional data bus. dqs, (dqs ) (ldqs), (ldqs ) (udqs), (udqs ) input/out- put data strobe: output with read data, input with write data. edge-aligned with read data, centered in write data. for the x16, ldqs corresponds to the data on dq0-dq7; udqs co rresponds to the data on dq8-dq15. the data strobes dqs, ldqs and udqs may be used in single ended mode or paired with optional complementary signals dqs , ldqs and udqs to provide differential pair sig naling to the system during both reads and writes. an emrs(1) control bit enables or disables all complementary data strobe signals. in this data sheet, "differential dqs signals" refers to any of the following with a10 = 0 of emrs(1) x16 ldqs/ldqs and udqs/udqs "single-ended dqs signals" refers to any of the following with a10 = 1 of emrs(1) x16 ldqs and udqs nc no connect: no internal electrical connection is present. v dd /v ddq supply power supply: 1.8v +/- 0.1v, dq power supply: 1.8v +/- 0.1v v ss /v ssq supply ground , dq ground v ddl supply dll power supply: 1.8v +/- 0.1v v ssdl supply dll ground v ref supply reference voltage
rev. 1.01 november 2007 ddr2 sdram k4t51163qe 512mb addressing * reference information: the following tables are address mapping information for other densities. 256mb 1gb 2gb 4gb configuration 128mb x4 64mb x 8 32mb x16 # of banks 4 4 4 bank address ba0,ba1 ba0,ba1 ba0,ba1 auto precharge a 10 /ap a 10 /ap a 10 /ap row address a 0 ~ a 13 a 0 ~ a 13 a 0 ~ a 12 column address a 0 ~ a 9, a 11 a 0 ~ a 9 a 0 ~ a 9 configuration 64mb x4 32mb x 8 16mb x16 # of banks 4 4 4 bank address ba0,ba1 ba0,ba1 ba0,ba1 auto precharge a 10 /ap a 10 /ap a 10 /ap row address a 0 ~ a 12 a 0 ~ a 12 a 0 ~ a 12 column address a 0 ~ a 9, a 11 a 0 ~ a 9 a 0 ~ a 8 configuration 256mb x4 128mb x 8 64mb x16 # of banks 8 8 8 bank address ba0 ~ ba2 ba0 ~ ba2 ba0 ~ ba2 auto precharge a 10 /ap a 10 /ap a 10 /ap row address a 0 ~ a 13 a 0 ~ a 13 a 0 ~ a 12 column address a 0 ~ a 9, a 11 a 0 ~ a 9 a 0 ~ a 9 configuration 512mb x4 256mb x 8 128mb x16 # of banks 8 8 8 bank address ba0 ~ ba2 ba0 ~ ba2 ba0 ~ ba2 auto precharge a 10 /ap a 10 /ap a 10 /ap row address a 0 ~ a 14 a 0 ~ a 14 a 0 ~ a 13 column address a 0 ~ a 9, a 11 a 0 ~ a 9 a 0 ~ a 9 configuration 1 gb x4 512mb x 8 256mb x16 # of banks 8 8 8 bank address ba0 ~ ba2 ba0 ~ ba2 ba0 ~ ba2 auto precharge a 10 /ap a 10 /ap a 10 /ap row address a 0 - a 15 a 0 - a 15 a 0 - a 14 column address/page size a 0 - a 9, a 11 a 0 - a 9 a 0 - a 9
rev. 1.01 november 2007 ddr2 sdram k4t51163qe absolute maximum dc ratings note : 1. stresses greater than those listed under ?absolute maximum rati ngs? may cause permanent damage to the device. this is a stre ss rating only and functional operation of the device at these or any other conditi ons above those indicated in the operational sections of this s pecification is not implied. exposure to absolute maximum rating condition s for extended periods may affect reliability. 2. storage temperature is the case surface temperature on the c enter/top side of the dram. for t he measurement conditions, plea se refer to jesd51-2 standard. ac & dc operating conditions recommended dc operating conditions (sstl - 1.8) note : there is no specific device v dd supply voltage requirement for sstl-1.8 compliance. however under all conditions v ddq must be less than or equal to v dd . 1. the value of v ref may be selected by the user to provide optimum noise margin in the system. typically the value of v ref is expected to be about 0.5 x v ddq of the transmitting device and v ref is expected to track variations in v ddq . 2. peak to peak ac noise on v ref may not exceed +/-2% v ref (dc). 3. v tt of transmitting device must track v ref of receiving device. 4. ac parameters are measured with v dd , v ddq and v ddl tied together. symbol parameter rating units notes v dd voltage on v dd pin relative to v ss - 1.0 v ~ 2.3 v v 1 v ddq voltage on v ddq pin relative to v ss - 0.5 v ~ 2.3 v v 1 v ddl voltage on v ddl pin relative to v ss - 0.5 v ~ 2.3 v v 1 v in, v out voltage on any pin relative to v ss - 0.5 v ~ 2.3 v v 1 t stg storage temperature -55 to +100 c 1, 2 symbol parameter rating units notes min. typ. max. v dd supply voltage 1.7 1.8 1.9 v v ddl supply voltage for dll 1.7 1.8 1.9 v 4 v ddq supply voltage for output 1.7 1.8 1.9 v 4 v ref input reference voltage 0.49*v ddq 0.50*v ddq 0.51*v ddq mv 1,2 v tt termination voltage v ref -0.04 v ref v ref +0.04 v 3
rev. 1.01 november 2007 ddr2 sdram k4t51163qe operating temperature condition 1. operating temperature is the case temperature on the dram input dc lo gic level input ac lo gic level ac input test conditions notes: 1. input waveform timing is referenced to the input signal crossing through the v ih/il (ac) level applied to the device under test. 2. the input signal minimum slew rate is to be maintained over the range from v ref to v ih (ac) min for rising edges and the range from v ref to v il (ac) max for falling edges as shown in the below figure. 3. ac timings are referenced with input waveforms switching from v il (ac) to v ih (ac) on the positive transitions and v ih (ac) to v il (ac) on the negative transitions. symbol parameter rating units notes toper operating temperature -40 to 95 c 1 symbol parameter min. max. units notes v ih (dc) dc input logic high v ref + 0.125 v ddq + 0.3 v v il (dc) dc input logic low - 0.3 v ref - 0.125 v symbol parameter ddr2-400, ddr2-533 ddr2-667, ddr2-800 units min. max. min. max. v ih (ac) ac input logic high v ref + 0.250 - v ref + 0.200 v v il (ac) ac input logic low -v ref - 0.250 v ref - 0.200 v symbol condition value units notes v ref input reference voltage 0.5 * v ddq v1 v swing(max) input signal maximum peak to peak swing 1.0 v 1 slew input signal minimum slew rate 1.0 v/ns 2, 3 v ddq v ih (ac) min v ih (dc) min v ref v il (dc) max v il (ac) max v ss < ac input test signal waveform > v swing(max) delta tr delta tf v ref - v il (ac) max delta tf falling slew = rising slew = v ih (ac) min - v ref delta tr
rev. 1.01 november 2007 ddr2 sdram k4t51163qe differential input ac logic level notes: 1. v id (ac) specifies the input differential voltage |v tr -v cp | required for switching, where v tr is the true input signal (such as ck, dqs, ldqs or udqs) and v cp is the complementary input signal (such as ck , dqs , ldqs or udqs ). the minimum value is equal to v ih (ac) - v il (ac). 2. the typical value of v ix (ac) is expected to be about 0.5 * v ddq of the transmitting device and v ix (ac) is expected to trac k variations in vddq . v ix (ac) indicates the voltage at which differential input signals must cross. differential ac output parameters note : 1. the typical value of v ox (ac) is expected to be about 0.5 * v ddq of the transmitting device and v ox (ac) is expected to trac k variations in vddq . v ox (ac) indicates the voltage at which differential output signals must cross. odt dc electrical characteristics note1: test condition for rtt measurements measurement definition for rtt(eff): apply v ih (ac) and v il (ac) to test pin separately, then measure current i(v ih (ac)) and i( v il (ac)) respectively. v ih (ac), v il (ac), and vddq values defined in sstl_18 measurement definition for vm: measure voltage (v m ) at test pin (midpoint) with no load. symbol parameter min. max. units notes v id(ac) ac differential input voltage 0.5 v ddq + 0.6 v 1 v ix(ac) ac differential cross point voltage 0.5 * vddq - 0.175 0.5 * vddq + 0.175 v 2 symbol parameter min. max. units note v ox (ac) ac differential cross point voltage 0.5 * vddq - 0.125 0.5 * vddq + 0.125 v 1 parameter/condition symbol min nom max units notes rtt effective impedance value for emrs(a6,a2)=0,1; 75 ohm rtt1(eff) 60 75 90 ohm 1 rtt effective impedance value for emrs(a6,a2)=1,0; 150 ohm rtt2(eff) 120 150 180 ohm 1 rtt effective impedance value for emrs(a6,a2)=1,1; 50 ohm rtt3(eff) 40 50 60 ohm 1 deviation of vm with respect to vddq/2 delta vm - 6 + 6 % 1 v ddq crossing point v ssq v tr v cp v id v ix or v ox < differential signal levels > rtt(eff) = v ih (ac) - v il (ac) i( v ih (ac) ) - i( v il (ac) ) delta vm = 2 x vm vddq x 100% - 1
rev. 1.01 november 2007 ddr2 sdram k4t51163qe ocd default characteristics notes: 1. absolute specifications (-40c t case +95c; vdd = +1.8v 0.1v, vddq = +1.8v 0.1v) 2. impedance measurement condition for output s ource dc current: vddq = 1.7v; vout = 1420mv; (vout-vddq)/ioh must be less than 23.4 ohms for values of vout between vddq and vddq- 280mv. impedance measurement condition for output sink dc current: vddq = 1.7v; vout = 28 0mv; vout/iol must be less than 23.4 ohms for values of vout between 0v and 280mv. 3. mismatch is absolute value between pull-up and pul l-dn, both are measured at same temperature and voltage. 4. slew rate measured from v il (ac) to v ih (ac). 5. the absolute value of the slew rate as measured from dc to dc is equal to or greater than the slew rate as measured from ac to ac. this is guaran- teed by design and characterization. 6. this represents the step size when the ocd is near 18 ohms at nominal conditions across all process and represents only the dram uncertainty. output slew rate load : 7. dram output slew rate specification applies to 400mb/sec/ pin, 533mb/sec/pin, 667mb/sec/ pin and 800mb/sec/pin speed bins. 8. timing skew due to dram output slew rate mis-match between dqs / dqs and associated dqs is included in tdqsq and tqhs specification. description parameter min nom max unit notes output impedance normal 18ohms see full strength default driver characteristics ohms 1,2 output impedance step size for ocd calibration 0 1.5 ohms 6 pull-up and pull-down mismatch 0 4 ohms 1,2,3 output slew rate sout 1.5 5 v/ns 1,4,5,6,7,8 25 ohms v tt output (v out) reference point
rev. 1.01 november 2007 ddr2 sdram k4t51163qe idd specification parame ters and test conditions (idd values are for full operating range of voltage and temperature, notes 1 - 5) symbol proposed conditions units notes idd0 operating one bank active-precharge current ; t ck = t ck(idd), t rc = t rc(idd), t ras = t rasmin(idd); cke is high, cs\ is high between valid commands; address bus inputs are switching; data bus inputs are switching ma idd1 operating one bank active-read-precharge current ; iout = 0ma; bl = 4, cl = cl(idd), al = 0; t ck = t ck(idd), t rc = t rc (idd), t ras = t rasmin(idd), t rcd = t rcd(idd); cke is high, cs\ is high between valid commands; address businputs are switching; data pat- tern is same as idd4w ma idd2p precharge power-down current ; all banks idle; t ck = t ck(idd); cke is low; other control and addres s bus inputs are stable; data bus inputs are floating ma idd2q precharge quiet standby current ; all banks idle; t ck = t ck(idd); cke is high, cs\ is high; other control and address bus inputsare stable; data bus inputs are floating ma idd2n precharge standby current ; all banks idle; t ck = t ck(idd); cke is high, cs\ is high; other c ontrol and address bus inputs are switching; data bus inputs are switching ma idd3p active power-down current ; all banks open; t ck = t ck(idd); cke is low; other control and address bus inputs are stable; data bus inputs are floating fast pdn exit mrs(12) = 0ma ma slow pdn exit mrs(12) = 1ma ma idd3n active standby current ; all banks open; t ck = t ck(idd), t ras = t rasmax(idd), t rp = t rp(idd); cke is high, cs\ is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching ma idd4w operating burst write current ; all banks open, continuous burst writes; bl = 4, cl = cl(idd), al = 0; t ck = t ck(idd), t ras = t rasmax(idd), t rp = t rp(idd); cke is high, cs\ is high between valid co mmands; address bus inputs are switching; data bus inputs are switching ma idd4r operating burst read current ; all banks open, continuous burst reads, iout = 0ma; bl = 4, cl = cl(idd), al = 0; t ck = t ck(idd), t ras = t ras- max(idd), t rp = t rp(idd); cke is high, cs\ is high between valid commands; address bus inputs are switch- ing; data pattern is same as idd4w ma idd5b burst auto refresh current ; t ck = t ck(idd); refresh command at every t rfc(idd) interval; cke is high, cs\ is high between valid com- mands; other control and address bus inputs are switching; data bus inputs are switching ma idd6 self refresh current ; ck and ck\ at 0v; cke 0.2v; other control and address bus inputs are floating; data bus inputs are floating normal ma low power ma idd7 operating bank interleave read current ; all bank interleaving reads, iout = 0ma; bl = 4, cl = cl(idd), al = t rcd(idd)-1* t ck(idd); t ck = t ck(idd), t rc = t rc(idd), t rrd = t rrd(idd), t faw = t faw(idd), t rcd = 1* t ck(idd); cke is high, cs\ is high between valid commands; address bus inputs are stable during deselects; data pattern is same as idd4r; refer to the fol- lowing page for detailed timing conditions ma
rev. 1.01 november 2007 ddr2 sdram k4t51163qe notes : 1. idd specifications are tested afte r the device is properly initialized 2. input slew rate is specified by ac parametric test condition 3. idd parameters are specified with odt disabled. 4. data bus consists of dq, dm, dqs, dqs \, ldqs, ldqs\, udqs, and udqs\. idd values must be met with all combinations of emrs b its 10 and 11. 5. definitions for idd low is defined as vin vilac(max) high is defined as vin vihac(min) stable is defined as inputs stable at a high or low level floating is defined as inputs at vref = vddq/2 switching is defined as: inputs changing bet ween high and low every other clock cycl e (once per two clocks) for address and control signals, and inputs changing between high and low every other data transfer (once per clock) for dq signals not includi ng masks or strobes. for purposes of idd test ing, the following pa rameters are utilized detailed idd7 the detailed timings are shown below for idd7. legend: a = active; ra = read with autoprecharge; d = deselect idd7: operating current: all bank interleave read operation all banks are being interleaved at minimum t rc(idd) without violating t rrd(idd) and t faw(idd) using a burst length of 4. control and address bus inputs are stable during deselects. iout = 0ma timing patterns for 4 bank devices x4/ x8/ x16 -ddr2-400 3/3/3 a0 ra0 a1 ra1 a2 ra2 a3 ra3 d d d -ddr2-533 4/4/4 a0 ra0 d a1 ra1 d a2 ra2 d a3 ra3 d d d d d -ddr2-667 5/5/5 a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d d d d -ddr2-667 4/4/4 a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d d d -ddr2-800 5/5/5 a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d d d d d d d ddr2-800 ddr2-667 ddr2-533 ddr2-400 units parameter 5-5-5 5-5-5 4-4-4 3-3-3 cl(idd) 5 5 4 3 tck t rcd(idd) 12.5 15 15 15 ns t rc(idd) 57.5 60 60 55 ns t rrd(idd)-x16 10 10 10 10 ns t ck(idd) 2.5 3 3.75 5 ns t rasmin(idd) 45 45 45 40 ns t rp(idd) 12.5 15 15 15 ns t rfc(idd) 105 105 105 105 ns
rev. 1.01 november 2007 ddr2 sdram k4t51163qe ddr2 sdram idd spec table symbol 32mx16 (k4t51163qe) unit 800@cl=6 667@cl=5 533@cl=4 400@cl=3 ie7 pe7 ie6 pe6 de6 id5 pd5 icc pcc idd0 95 90 90 90 ma idd1 115 110 105 105 ma idd2p 8 8 8 8 ma idd2q 35 35 30 30 ma idd2n 40 40 35 35 ma idd3p-f 30 30 30 30 ma idd3p-s 12 12 12 12 ma idd3n 60 55 50 50 ma idd4w 135 120 105 100 ma idd4r 190 170 140 135 ma idd5 115 110 110 110 ma idd6 848438484ma idd7 280 240 240 215 ma
rev. 1.01 november 2007 ddr2 sdram k4t51163qe input/output capacitance electrical characteristi cs & ac timing for ddr2-800/667/533/400 (-40 c < t case < 95 c; v ddq = 1.8v + 0.1v; v dd = 1.8v + 0.1v) refresh parameters by device density speed bins and cl, trcd, trp, trc and tras for corresponding bin parameter symbol ddr2-400 ddr2-533 ddr2-667 ddr2-800 units min max min max min max input capacitance, ck and ck cck 1.0 2.0 1.0 2.0 1.0 2.0 pf input capacitance delta, ck and ck cdck x 0.25 x 0.25 x 0.25 pf input capacitance, all other input-only pins ci 1.0 2.0 1.0 2.0 1.0 1.75 pf input capacitance delta, all other input-only pins cdi x 0.25 x 0.25 x 0.25 pf input/output capacitance, dq, dm, dqs, dqs cio 2.5 4.0 2.5 3.5 2.5 3.5 pf input/output capacitance delta, dq, dm, dqs, dqs cdio x 0.5 x 0.5 x 0.5 pf parameter symbol 256mb 512mb 1gb 2gb 4gb units refresh to active/refresh command time trfc 75 105 127.5 195 327.5 ns average periodic refresh interval trefi -40 c t case 95 c 7.8 7.8 7.8 7.8 7.8 s speed ddr2-800(e7) ddr2-667(e6) ddr2-533(d5) ddr2-400(cc) units bin (cl - trcd - trp) 5-5-5 5 - 5 - 5 4 - 4 - 4 3 - 3 - 3 parameter min max min max min max min max tck, cl=3 5 8 5 8 5 8 5 8 ns tck, cl=4 3 8 3.75 8 3.75 8 5 8 ns tck, cl=5 2.5 8 3 8 3.75 8 - - ns tck, cl=6 2.5 8 - - - - - - ns trcd 12.5 15 15 15 ns trp 12.5 15 15 15 ns trc 57.5 60 60 55 ns tras 45 70000 45 70000 45 70000 40 70000 ns
rev. 1.01 november 2007 ddr2 sdram k4t51163qe timing parameters by speed grade (refer to notes for informations related to this table at the bottom) parameter symbol ddr2-800 ddr2-667 ddr2-533 ddr2-400 units notes min max min max min max min max dq output access time from ck/ck tac - 400 400 -450 +450 -500 +500 -600 +600 ps dqs output access time from ck/ck tdqsck - 350 350 -400 +400 -450 +450 -500 +500 ps ck high-level width tch 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tck ck low-level width tcl 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tck ck half period thp min(tcl,t ch) x min(tcl, tch) x min(tcl, tch) x min(tcl, tch) x ps 20,21 clock cycle time, cl=x tck 2500 8000 3000 8000 3750 8000 5000 8000 ps 24 dq and dm input hold time tdh(base) 125 x 175 x 225 x 275 x ps 15,16, 17,20 dq and dm input setup time tds(base) 50 x 100 x 100 x 150 x ps 15,16, 17,21 control & address input pulse width for each input tipw 0.6 x 0.6 x 0.6 x0.6 x tck dq and dm input pulse width for each input tdipw 0.35 x 0.35 x 0.35 x0.35 x tck data-out high-impedance time from ck/ck thz x tac max x tac max x tac max x tac max ps dqs low-impedance time from ck/ck tlz(dqs) tac min tac max tac min tac max tac min tac max tac min tac max ps 27 dq low-impedance time from ck/ck tlz(dq) 2* tac min tac max 2*tac min tac max 2* tacmin tac max 2* tacmin tac max ps 27 dqs-dq skew for dqs and associated dq sig- nals tdqsq x 200 x 240 x 300 x 350 ps 22 dq hold skew factor tqhs x 300 x 340 x 400 x 450 ps 21 dq/dqs output hold time from dqs tqh thp - tqhs x thp - tqhs x thp - tqhs x thp - tqhs x ps first dqs latching transition to associated clock edge tdqss - 0.25 0.25 -0.25 0.25 -0.25 0.25 -0.25 0.25 tck dqs input high pulse width tdqsh 0.35 x 0.35 x 0.35 x 0.35 x tck dqs input low pulse width tdqsl 0.35 x 0.35 x 0.35 x 0.35 x tck dqs falling edge to ck setup time tdss 0.2 x 0.2 x 0.2 x 0.2 x tck dqs falling edge hold time from ck tdsh 0.2 x 0.2 x 0.2 x 0.2 x tck mode register set command cycle time tmrd 2 x 2 x 2 x 2 x tck write postamble twpst 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tck 19 write preamble twpre 0.35 x 0.35 x 0.35 x 0.35 x tck address and control input hold time tih(base) 250 x 275 x 375 x 475 x ps 14,16, 18,23 address and control input setup time tis(base) 175 x 200 x 250 x 350 x ps 14,16, 18,22 read preamble trpre 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 tck 28 read postamble trpst 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tck 28 active to active command period for 1kb page size products trrd 7.5 x 7.5 x7.5 x 7.5 x ns 12
rev. 1.01 november 2007 ddr2 sdram k4t51163qe parameter symbol ddr2-800 ddr2-667 ddr2-533 ddr2-400 units notes min max min max min max min max active to active command period for 2kb page size products trrd 10 x 10 x10 x 10 x ns 12 four activate window fo r 1kb page size products tfaw 35 37.5 37.5 37.5 ns four activate window fo r 2kb page size products tfaw 45 50 50 50 ns cas to cas command delay tccd 2 x 2 2 2 tck write recovery time twr 15 x 15 x15 x 15 x ns auto precharge write recovery + precharge time tdal wr+trp x wr+trp x wr+trp x wr+trp x tck 23 internal write to read command delay twtr 7.5 7.5 x7.5 x10 x ns 33 internal read to precharge command delay trtp 7.5 7.5 7.5 7.5 ns 11 exit self refresh to a non-read command txsnr trfc + 10 trfc + 10 trfc + 10 trfc + 10 ns exit self refresh to a read command txsrd 200 x 200 200 200 tck exit precharge power down to any non-read com- mand txp 2 x 2 x 2 x 2 x tck exit active power down to read command txard 2 x 2 x 2 x 2 x tck 9 exit active power down to read command (slow exit, lower power) txards 8 - al 7 - al 6 - al 6 - al tck 9, 10 cke minimum pulse width (high and low pulse width) t cke 3 3 33tck36 odt turn-on delay t aond22222222tck odt turn-on t aon tac(min) tac(max) + 0.7 tac(min) tac(max) +0.7 tac(min) tac(max) +1 tac(min) tac(max) +1 ns 13, 25 odt turn-on(power-down mode) t aonpd tac(min)+ 2 2tck + tac(max) +1 tac(min)+ 2 2tck+tac (max)+1 tac(min)+ 2 2tck+ta c(max)+ 1 tac(min)+ 2 2tck+tac (max)+1 ns odt turn-off delay t aofd 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 tck odt turn-off t aof tac(min) tac(max) + 0.6 tac(min) tac(max) + 0.6 tac(min) tac(max) + 0.6 tac(min) tac(max) + 0.6 ns 26 odt turn-off (power-down mode) t aofpd tac(min)+ 2 2.5tck + tac(max) +1 tac(min)+ 2 2.5tck+t ac(max) +1 tac(min)+ 2 2.5tck+ tac(max) +1 tac(min)+ 2 2.5tck+ tac(max) +1 ns odt to power down entry latency tanpd 3 3 3 3 tck odt power down exit latency taxpd 8 8 8 8 tck ocd drive mode output delay toit 0 12 0 12 0 12 0 12 ns minimum time clocks remains on after cke asyn- chronously drops low tdelay tis+tck +tih tis+tck +tih tis+tck +tih tis+tck +tih ns 24
rev. 1.01 november 2007 ddr2 sdram k4t51163qe general notes, which may a pply for all ac parameters 1. slew rate measurement levels a. output slew rate for falling and rising edges is measured between vtt - 250 mv and vtt + 250 mv for single ended signals. for differential signals (e.g. dqs - dqs ) output slew rate is measured between dqs - dqs = -500 mv and dqs - dqs = +500mv. output slew rate is guaranteed by design, but is not necessarily tested on each device. b. input slew rate for single ended signals is measured from dc-level to ac-level: from vil(dc) to vih(ac) for rising edges and from vih(dc) and vil(ac) for falling edges. for differential signals (e.g. ck - ck ) slew rate for rising edges is measured from ck - ck = -250 mv to ck - ck = +500 mv (250mv to -500 mv for falling edges). c. vid is the magnitude of the difference between the input voltage on ck and the input voltage on ck , or between dqs and dqs for differential strobe. 2. ddr2 sdram ac timing reference load following figure represents the timing reference load used in def ining the relevant timing parameters of the part. it is not in tended to be either a precise representation of the typical system envir onment or a depiction of the actual load pr esented by a production tester. system desi gners will use ibis or other simulation tools to correlate the timing reference load to a system environment. manufacturers will correlate to their pr oduction test conditions (gen- erally a coaxial transmission line te rminated at the tester electronics). the output timing reference voltage level for single ended signals is the crosspoint with vtt. the output timing reference volt age level for differential sig- nals is the crosspoint of the true (e.g. dq s) and the complement (e.g. dqs) signal. 3. ddr2 sdram output slew rate test load output slew rate is characterized under the te st conditions as shown in the following figure. vddq dut dq dqs dqs output v tt = v ddq /2 25 ? timing reference point vddq dut dq dqs, dqs output v tt = v ddq /2 25 w test point
rev. 1.01 november 2007 ddr2 sdram k4t51163qe 4. differential data strobe ddr2 sdram pin timings are specified for either single ended mode or differential m ode depending on the setting of the emrs ?en able dqs? mode bit; timing advantages of differential mode are realized in system design. the method by which the ddr2 sdram pin timings are m easured is mode dependent. in single ended mode, timing relationships are measured rela tive to the rising or fallin g edges of dqs crossing at v ref. in differential mode, these timing relationships are measured relative to the crosspoint of dqs and its complement, dqs . this distinction in timing methods is guar- anteed by design and characterization. note t hat when differential data strobe mode is disabled via the emrs, the complementary pin, dqs , must be tied externally to vss through a 20 ohm to 10 k ohm resisor to insure proper operation. 5. ac timings are for linear signal transitions. 6. these parameters guarantee device behavior, but they are not necessarily tested on each device. they may be guaranteed by de vice design or tester correlation. 7. all voltages are referenced to vss. 8. tests for ac timing, idd, and electrical (ac and dc) characte ristics, may be conducted at nom inal reference/supply voltage l evels, but the related specifications and device operation are gua ranteed for the full voltage range specified. t ds t ds t dh t wpre t wpst t dqsh t dqsl dqs dqs d dmin dqs/ dq dm t dh dmin dmin dmin d d d dqs v il (ac) v ih (ac) v il (ac) v ih (ac) v il (dc) v ih (dc) v il (dc) v ih (dc) t ch t cl ck ck ck/ck dqs/dqs dq dqs dqs t rpst q t rpre t dqsqmax t qh t qh t dqsqmax q qq
rev. 1.01 november 2007 ddr2 sdram k4t51163qe specific notes for dedicated ac parameters 9. user can choose which active power down exit timing to use via mrs(bit 12). txard is expected to be used for fast active pow er down exit timing. txards is expected to be used for sl ow active power down exit timing. 10. al = additive latency 11. this is a minimum requirement. minimum read to precharge timi ng is al + bl/2 providing the trtp and tras(min) have been sat isfied. 12. for ddr2-533/400, a minimum of two clocks (2 *tck) is required irrespective of operating frequency. for ddr2-800/667, tnparam=ru{tparam / tck(avg)}, whic h is in clock cycles, assuming all input clock jitter specification are satisfied. 13. timings are guaranteed with command/address input slew rate of 1.0 v/ns. 14. these parameters guarantee device behavior, but they are not necessarily tested on each dev ice. they may be guaranteed by d evice design or tester correlation. 15. timings are guaranteed with data, mask, and (dqs in singled ended mode) input slew rate of 1.0 v/ns. 16. timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. timings are guaranteed for dqs signals with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1v/ns in single ended mode. 17. tds and tdh derating values for all input signals the total tds (setup time) and tdh(hold time ) required is calculated by adding the datasheet tds(base) an d tdh(base) value to the delta tds and delta tdh derating value respectively. exam ple: tds(total setup time)= tds(base) + delta tds. ? tds, ? tdh derating values of ddr2-400, ddr2-533 (all units in ?ps?, note 1 applies to entire table) dqs,dqs differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4v/ns 1.2v/ns 1.0v/ns 0.8v/ns ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh dq siew rate v/ns 2.0 125 45 125 45 125 45 - - - - - - - - - - - - 1.58321832183219533---------- 1.0 0 0 0 0 0 0 12 12 24 24 - - - - - - - - 0.9 - - -11 -14 -11 -14 1 -2 13 10 25 22 - - - - - - 0.8 - - - - -25 -31 -13 -19 -1 -7 11 5 23 17 - - - - 0.7 - - - - - - -31 -42 -19 -30 -7 -18 5 -6 17 6 - - 0.6---------43-59-31-47-19-35-7-235-11 0.5-----------74-89-62-77-50-65-38-53 0.4 - - - - - - - - - - - - -127 -140 -115 -128 -103 -116 ? tds, ? tdh derating values for ddr2-667, ddr2-800 (all units in ?ps?, note 1 applies to entire table) dqs,dqs differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4v/ns 1.2v/ns 1.0v/ns 0.8v/ns ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh dq slew rate v/ns 2.0 100 45 100 45 100 45 - - - - - - - - - - - - 1.56721672167217933 - - - - - - - - - - 1.000000012122424- - - - - - - - 0.9 - - -5 -14 -5 -14 7 -2 19 10 31 22 - - - - - - 0.8 - - - - -13 -31 -1 -19 11 -7 23 5 35 17 - - - - 0.7-------10-422-3014-1826-6386-- 0.6---------10-592-4714-3526-2338-11 0.5-----------24-89-12-770-6512-53 0.4-------------52-140-40-128-28-116
rev. 1.01 november 2007 ddr2 sdram k4t51163qe for all input signals the total tis (setup time) and tih(hold time) required is calcul ated by adding the datasheet tis(base) an d tih(base) value to the delta tis and delta tih derating value respectively. exampl e: tis(total setup time)= tis(base) + delta tis. ? tds1, ? tdh1 derating values for ddr2-400, ddr2-533(all units in ?ps?; the note applies to the entire table) dqs single-ended slew rate 2.0 v/ns 1.5 v/ns 1.0 v/ns 0.9 v/ns 0.8 v/ns 0.7 v/ns 0.6 v/ns 0.5 v/ns 0.4 v/ns ? tds 1 ? tdh 1 ? tds 1 ? tdh 1 ? tds 1 ? tdh 1 ? tds 1 ? tdh 1 ? tds 1 ? tdh 1 ? tds 1 ? tdh 1 ? tds 1 ? tdh 1 ? tds 1 ? tdh 1 ? tds 1 ? tdh 1 dq slew rate v/ns 2.018818816714612563------------ 1.514616712512583428143---------- 1.063125428300-21-7-13-------- 0.9--3169-11-14-13-13-18-27-29-45------ 0.8-----25-31-27-30-32-44-43-62-60-86---- 0.7-------45-53-50-67-61-85-78-109-108-152-- 0.6---------74-96-85-114-102-138-138-181-183-246 0.5-----------128-156-145-180-175-223-226-288 0.4-------------210-243-240-286-291-351
rev. 1.01 november 2007 ddr2 sdram k4t51163qe 18. tis and tih (input setup and hold) derating. for all input signals the total tis (setup time) and tih(hold time) required is calcul ated by adding the datasheet tis(base) an d tih(base) value to the delta tis and delta tih derating value respectively. exampl e: tis(total setup time)= tis(base) + delta tis. ? tis, ? tih derating values for ddr2-400, ddr2-533 ck, ck differential slew rate 2.0 v/ns 1.5 v/ns 1.0 v/ns units notes ? tis ? tih ? tis ? tih ? tis ? tih command/ address slew rate(v/ns) 4.0 +187 +94 +217 +124 +247 +154 ps 1 3.5 +179 +89 +209 +119 +239 +149 ps 1 3.0 +167 +83 +197 +113 +227 +143 ps 1 2.5 +150 +75 +180 +105 +210 +135 ps 1 2.0 +125 +45 +155 +75 +185 +105 ps 1 1.5 +83 +21 +113 +51 +143 +81 ps 1 1.0 0 0 +30 +30 +60 +60 ps 1 0.9 -11 -14 +19 +16 +49 +46 ps 1 0.8 -25 -31 +5 -1 +35 +29 ps 1 0.7 -43 -54 -13 -24 +17 +6 ps 1 0.6 -67 -83 -37 -53 -7 -23 ps 1 0.5 -110 -125 -80 -95 -50 -65 ps 1 0.4 -175 -188 -145 -158 -115 -128 ps 1 0.3 -285 -292 -255 -262 -225 -232 ps 1 0.25 -350 -375 -320 -345 -290 -315 ps 1 0.2 -525 -500 -495 -470 -465 -440 ps 1 0.15 -800 -708 -770 -678 -740 -648 ps 1 ? tis and ? tih derating values for ddr2-667, ddr2-800 ck, ck differential slew rate 2.0 v/ns 1.5 v/ns 1.0 v/ns units notes ? tis ? tih ? tis ? tih ? tis ? tih command/ address slew rate(v/ns) 4.0 +150 +94 +180 +124 +210 +154 ps 1 3.5 +143 +89 +173 +119 +203 +149 ps 1 3.0 +133 +83 +163 +113 +193 +143 ps 1 2.5 +120 +75 +150 +105 +180 +135 ps 1 2.0 +100 +45 +130 +75 +160 +105 ps 1 1.5 +67 +21 +97 +51 +127 +81 ps 1 1.0 0 0 +30 +30 +60 +60 ps 1 0.9 -5 -14 +25 +16 +55 +46 ps 1 0.8 -13 -31 +17 -1 +47 +29 ps 1 0.7 -22 -54 +8 -24 +38 +6 ps 1 0.6 -34 -83 -4 -53 +26 -23 ps 1 0.5 -60 -125 -30 -95 0 -65 ps 1 0.4 -100 -188 -70 -158 -40 -128 ps 1 0.3 -168 -292 -138 -262 -108 -232 ps 1 0.25 -200 -375 -170 -345 -140 -315 ps 1 0.2 -325 -500 -295 -470 -265 -440 ps 1 0.15 -517 -708 -487 -678 -457 -648 ps 1 0.1 -1000 -1125 -970 -1095 -940 -1065 ps 1
rev. 1.01 november 2007 ddr2 sdram k4t51163qe 19. the maximum limit for this parameter is not a device limit. the device will operate with a greater value for this parameter , but system performance (bus turnaround) will degrade accordingly. 20. min ( tcl, tch) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification li mits for tcl and tch). for example, tcl and tch are = 50% of the period, less the half period jitter ( tjit(hp)) of the clock source, and less the half period jitter due to crosstalk ( tjit(crosstalk )) into the clock traces. 21. tqh = thp ? tqhs, where: thp = minimum half clock period for any given cycle and is defi ned by clock high or cl ock low ( tch, tcl). tqhs accounts for: 1) the pulse duration distortion of on-chip clock circuits; and 2) the worst case push-out of dqs on one transition followed by the worst case pull-in of dq on the next transition, both of wh ich are, separately, due to data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers. 22. tdqsq: consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output slew rate mismatch between dqs / dqs and associated dq in any given cycle. 23. tdal = wr + ru{trp(ns)/tck(ns)}, where ru stands for round up. wr refers to the twr parameter stored in the mrs. for trp, if the result of the division is not already an integer, round up to the next highest integer. tck refers to the application clock period. example: for ddr533 at tck = 3.75ns with twr programmed to 4 clocks. tdal = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks. 24. the clock frequency is allowed to change during self?refresh mode or precharge power-down mode. in case of clock frequency change during pre- charge power-down, a specific procedure is r equired as described in ddr2 device operation 25. odt turn on time min is when the device leaves high impedance and odt resistance begins to turn on. odt turn on time max is when the odt resi stance is fully on. both are measured from taond. 26. odt turn off time min is when the device starts to turn off odt resistance. odt turn off time max is when the bus is in high impedance. both are measured from taofd. 27. thz and tlz transitions occur in the same access time as vali d data transitions. these parameters are referenced to a speci fic voltage level which specifies when the device output is no longer driving (thz), or begins driving (tlz). following figure shows a method to calcul ate the point when device is no longer driving (thz), or begins driving (tlz) by measuring the signal at two different voltages. the actual voltag e measurement points are not critical as long as t he calculation is consistent. 28. trpst end point and trpre begin point are not referenced to a specific voltage level but specify when the device output is no longer driving (trpst), or begins driving (trpre). following figure shows a method to ca lculate these points when the devi ce is no longer driving (trps t), or begins driving (trpre) by measuring the signal at two different voltages. the ac tual voltage measurement points ar e not critical as long as th e calculation is consis- tent. these notes are referenced in the ?timing parameters by speed grade? tables for ddr2-400/533/667 and ddr2-800.
rev. 1.01 november 2007 ddr2 sdram k4t51163qe 29. input waveform timing with differential data strobe enabled mr [bit10]=0, is referenced from the input signal crossing at th e v ih(ac) level to the differen- tial data strobe crosspoint for a rising signal, and from the i nput signal crossing at the v il(ac) level to the differential data strobe crosspoint for a falling signal applied to the device under test. 30. input waveform timing with differential data strobe enabled mr [bit10]=0, is referenced from the input signal crossing at th e v ih(dc) level to the differen- tial data strobe crosspoint for a rising signal and v il(dc) to the differential data strobe crosspoint for a falling signal applied to the device under test. thz trpst end point t1 t2 voh + x mv voh + 2x mv vol + 2x mv vol + x mv tlz trpre begin point t2 t1 vtt + 2x mv vtt + x mv vtt - x mv vtt - 2x mv tlz,trpre begin point = 2*t1-t2 thz,trpst end point = 2*t1-t2 tds v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max v ss dqs dqs tdh tds tdh differential input waveform timing
rev. 1.01 november 2007 ddr2 sdram k4t51163qe 31. input waveform timing is referenced fr om the input signal crossing at the v ih(ac) level for a rising signal and v il(ac) for a falling signal applied to the device under test. 32. input waveform timing is referenced fr om the input signal crossing at the v il(dc) level for a rising signal and v ih(dc) for a falling signal applied to the device under test. 33. twtr is at lease two clocks (2 * tck) independent of operation frequency. 34. input waveform timing with single-ended data strobe enabled mr[bit 10] = 1, is referenced from the input signal crossing at the vih(ac) level to the single-ended data strobe crossing vih/l(dc) at the star t of its transition for a rising signal, and from the input signal crossing at the vil(ac) level to the single-ended data strobe crossing vih/l(dc) at the start of its transition for a falling signal applied to the device unde r test. the dqs signal must be monotonic between vil(dc)max and vih(dc)min. 35. input waveform timing with single-ended data strobe enabled mr[b it10] = 1, is referenced from the input signal crossing at the vih(dc) level to the single-ended data strobe crossing vih/l(ac) at the end of its transition for a rising signal, and from the input signal c rossing at the vil(dc) level to the single-ended data strobe crossing vih/l(ac) at the end of its transition for a falling signal applied to the device under test. the dqs signal must be monotonic between vil(dc)max and vih(dc)min. 36. tckemin of 3 clocks means cke must be registered on three c onsecutive positive cloc k edges. cke must remain at the valid in put level the entire time it takes to achieve the 3 cl ocks of registeration. thus, after any cke transition, cke may not transitioin from its valid level during the time period of tis + 2*tck + tih. tis v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max v ss ck ck tih tis tih

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